![]() ![]() |
||
SDC9 JudgesJim ZiobroRochester IEEE Student Activities ChairJames Ziobro has been an engineer for over 30 years. He has he has extensive experience in: complex software systems, real-time control, digital design, and image processing. In addition to industrial experience he has taught computer engineering courses. He holds three patents and has received numerous corporate awards. The Rochester Institute of Technology granted him a BS in Computer Engineering in 1979 and the University of Rochester granted a MS in Electrical Engineering in 1991. He continues to be involved in volunteer activities especially for the IEEE. He has been a Chapter Chair and Section for the Rochester Section and Western Area Chair for Region One. He has also been a conference and book reviewer. He is currently the Student Activities Chair for the Rochester Section and the Regional Chapters Coordinator for the Computer Society. Matt HicksMatt Hicks is an optical/microelectronical engineer at the National Secure Manufacturing Center within the Honeywell Kansas City Plant. His experience extends from thin film deposition/application, chemical detection/standoff detectors, fiber optics sensors and semiconductor processing. His personal hobbies are billiards and frisbee. He currently is the chairman of IEEE GOLD for Kansas City. Matt has represented GOLD and IEEE on the regional and national level. He also belongs to OSA and SPIE. John Turnergraduated from RIT with a bachelors in Computer Engineering in 2000. He has worked at Fairchild Semiconductor as a Staff Engineer for a little over 1 year. Previously, John worked at Tundra Semiconductor as a Design Engineer for 8 years. During his 9 years as an engineer, John has designed and verified complex digital integrated circuits including a four channel DMA engine, Intel XScale processor bus interface, PCIe and switch fabric memory management controllers, memory BIST engines, and an automatic charger detection state machine, John is currently leading a team of 4 engineers through a design enhancement and development phase for a very high volume production quality device.
|
||